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C/C++ Source or Header  |  2000-05-04  |  16KB  |  432 lines
  1. /****************************************************************************
  2.  
  3.     Exterminator memory map
  4.  
  5. driver by Zsolt Vasvari and Alex Pasadyn
  6.  
  7.  
  8.  Master CPU (TMS34010, all addresses are in bits)
  9.  
  10.  00000000-000fffff RW Video RAM (256x256x15)
  11.  00c00000-00ffffff RW RAM
  12.  01000000-010fffff  W Host Control Interface (HSTADRL)
  13.  01100000-011fffff  W Host Control Interface (HSTADRH)
  14.  01200000-012fffff RW Host Control Interface (HSTDATA)
  15.  01300000-013fffff  W Host Control Interface (HSTCTLH)
  16.  01400000-01400007 R  Input Port 0
  17.  01400008-0140000f R  Input Port 1
  18.  01440000-01440007 R  Input Port 2
  19.  01440008-0144000f R  Input Port 3
  20.  01480000-01480007 R  Input Port 4
  21.  01500000-0150000f  W Output Port 0 (See machine/exterm.c)
  22.  01580000-0158000f  W Sound Command
  23.  015c0000-015c000f  W Watchdog
  24.  01800000-01807fff RW Palette RAM
  25.  02800000-02807fff RW EEPROM
  26.  03000000-03ffffff R  ROM
  27.  3f000000-3fffffff R  ROM Mirror
  28.  c0000000-c00001ff RW TMS34010 I/O Registers
  29.  ff000000-ffffffff R  ROM Mirror
  30.  
  31.  
  32.  Slave CPU (TMS34010, all addresses are in bits)
  33.  
  34.  00000000-000fffff RW Video RAM (2 banks of 256x256x8)
  35.  c0000000-c00001ff RW TMS34010 I/O Registers
  36.  ff800000-ffffffff RW RAM
  37.  
  38.  
  39.  DAC Controller CPU (6502)
  40.  
  41.  0000-07ff RW RAM
  42.  4000      R  Sound Command
  43.  8000-8001  W 2 Channels of DAC output
  44.  8000-ffff R  ROM
  45.  
  46.  
  47.  YM2151 Controller CPU (6502)
  48.  
  49.  0000-07ff RW RAM
  50.  4000       W YM2151 Command/Data Register (Controlled by a bit A000)
  51.  6000          W NMI occurence rate (fed into a binary counter)
  52.  6800      R  Sound Command
  53.  7000      R  Causes NMI on DAC CPU
  54.  8000-ffff R  ROM
  55.  a000       W Control register (see sndhrdw/gottlieb.c)
  56.  
  57. ****************************************************************************/
  58.  
  59. #include "driver.h"
  60. #include "cpu/tms34010/tms34010.h"
  61.  
  62. static unsigned char *eeprom;
  63. static size_t eeprom_size;
  64. static size_t code_rom_size;
  65. unsigned char *exterm_code_rom;
  66.  
  67. extern unsigned char *exterm_master_speedup, *exterm_slave_speedup;
  68. extern unsigned char *exterm_master_videoram, *exterm_slave_videoram;
  69.  
  70. /* Functions in vidhrdw/exterm.c */
  71. void exterm_init_palette(unsigned char *palette, unsigned short *colortable,const unsigned char *color_prom);
  72. int  exterm_vh_start(void);
  73. void exterm_vh_stop (void);
  74. READ_HANDLER( exterm_master_videoram_r );
  75. READ_HANDLER( exterm_slave_videoram_r );
  76. WRITE_HANDLER( exterm_paletteram_w );
  77. void exterm_vh_screenrefresh(struct osd_bitmap *bitmap,int full_refresh);
  78. void exterm_to_shiftreg_master(unsigned int address, unsigned short* shiftreg);
  79. void exterm_from_shiftreg_master(unsigned int address, unsigned short* shiftreg);
  80. void exterm_to_shiftreg_slave(unsigned int address, unsigned short* shiftreg);
  81. void exterm_from_shiftreg_slave(unsigned int address, unsigned short* shiftreg);
  82.  
  83. /* Functions in sndhrdw/gottlieb.c */
  84. WRITE_HANDLER( gottlieb_sh_w );
  85. READ_HANDLER( gottlieb_cause_dac_nmi_r );
  86. WRITE_HANDLER( gottlieb_nmi_rate_w );
  87. WRITE_HANDLER( exterm_sound_control_w );
  88. WRITE_HANDLER( exterm_ym2151_w );
  89.  
  90. /* Functions in machine/exterm.c */
  91. WRITE_HANDLER( exterm_host_data_w );
  92. READ_HANDLER( exterm_host_data_r );
  93. READ_HANDLER( exterm_coderom_r );
  94. READ_HANDLER( exterm_input_port_0_1_r );
  95. READ_HANDLER( exterm_input_port_2_3_r );
  96. WRITE_HANDLER( exterm_output_port_0_w );
  97. READ_HANDLER( exterm_master_speedup_r );
  98. WRITE_HANDLER( exterm_slave_speedup_w );
  99. READ_HANDLER( exterm_sound_dac_speedup_r );
  100. READ_HANDLER( exterm_sound_ym2151_speedup_r );
  101.  
  102.  
  103. static void nvram_handler(void *file, int read_or_write)
  104. {
  105.     if (read_or_write)
  106.         osd_fwrite(file,eeprom,eeprom_size);
  107.     else
  108.     {
  109.         if (file)
  110.             osd_fread(file,eeprom,eeprom_size);
  111.         else
  112.             memset(eeprom,0,eeprom_size);
  113.     }
  114. }
  115.  
  116.  
  117. static struct tms34010_config master_config =
  118. {
  119.     0,                            /* halt on reset */
  120.     NULL,                        /* generate interrupt */
  121.     exterm_to_shiftreg_master,    /* write to shiftreg function */
  122.     exterm_from_shiftreg_master    /* read from shiftreg function */
  123. };
  124.  
  125.  
  126. static struct MemoryReadAddress master_readmem[] =
  127. {
  128.     { TOBYTE(0x00000000), TOBYTE(0x000fffff), exterm_master_videoram_r },
  129.     { TOBYTE(0x00c800e0), TOBYTE(0x00c800ef), exterm_master_speedup_r },
  130.     { TOBYTE(0x00c00000), TOBYTE(0x00ffffff), MRA_BANK1 },
  131.     { TOBYTE(0x01000000), TOBYTE(0x0100000f), MRA_NOP }, /* Off by one bug in RAM test, prevent log entry */
  132.     { TOBYTE(0x01200000), TOBYTE(0x012fffff), exterm_host_data_r },
  133.     { TOBYTE(0x01400000), TOBYTE(0x0140000f), exterm_input_port_0_1_r },
  134.     { TOBYTE(0x01440000), TOBYTE(0x0144000f), exterm_input_port_2_3_r },
  135.     { TOBYTE(0x01480000), TOBYTE(0x0148000f), input_port_4_r },
  136.     { TOBYTE(0x01800000), TOBYTE(0x01807fff), paletteram_word_r },
  137.     { TOBYTE(0x01808000), TOBYTE(0x0180800f), MRA_NOP }, /* Off by one bug in RAM test, prevent log entry */
  138.     { TOBYTE(0x02800000), TOBYTE(0x02807fff), MRA_BANK2 },
  139.     { TOBYTE(0x03000000), TOBYTE(0x03ffffff), exterm_coderom_r },
  140.     { TOBYTE(0x3f000000), TOBYTE(0x3fffffff), exterm_coderom_r },
  141.     { TOBYTE(0xc0000000), TOBYTE(0xc00001ff), TMS34010_io_register_r },
  142.     { TOBYTE(0xff000000), TOBYTE(0xffffffff), MRA_BANK3 },
  143.     { -1 }  /* end of table */
  144. };
  145.  
  146. static WRITE_HANDLER( placeholder )
  147. {}
  148.  
  149. static struct MemoryWriteAddress master_writemem[] =
  150. {
  151.     { TOBYTE(0x00000000), TOBYTE(0x000fffff), placeholder, &exterm_master_videoram },
  152. /*{ TOBYTE(0x00000000), TOBYTE(0x000fffff), exterm_master_videoram_16_w },     OR        */
  153. /*{ TOBYTE(0x00000000), TOBYTE(0x000fffff), exterm_master_videoram_8_w },                */
  154.     { TOBYTE(0x00c00000), TOBYTE(0x00ffffff), MWA_BANK1 },
  155.     { TOBYTE(0x00c800e0), TOBYTE(0x00c800ef), placeholder, &exterm_master_speedup },
  156.     { TOBYTE(0x01000000), TOBYTE(0x013fffff), exterm_host_data_w },
  157.     { TOBYTE(0x01500000), TOBYTE(0x0150000f), exterm_output_port_0_w },
  158.     { TOBYTE(0x01580000), TOBYTE(0x0158000f), gottlieb_sh_w },
  159.     { TOBYTE(0x015c0000), TOBYTE(0x015c000f), watchdog_reset_w },
  160.     { TOBYTE(0x01800000), TOBYTE(0x01807fff), exterm_paletteram_w, &paletteram },
  161.     { TOBYTE(0x02800000), TOBYTE(0x02807fff), MWA_BANK2, &eeprom, &eeprom_size }, /* EEPROM */
  162.     { TOBYTE(0xc0000000), TOBYTE(0xc00001ff), TMS34010_io_register_w },
  163.     { TOBYTE(0xff000000), TOBYTE(0xffffffff), MWA_BANK3, &exterm_code_rom, &code_rom_size },
  164.     { -1 }  /* end of table */
  165. };
  166.  
  167.  
  168. static struct tms34010_config slave_config =
  169. {
  170.     1,                            /* halt on reset */
  171.     NULL,                        /* generate interrupt */
  172.     exterm_to_shiftreg_slave,    /* write to shiftreg function */
  173.     exterm_from_shiftreg_slave    /* read from shiftreg function */
  174. };
  175.  
  176.  
  177. static struct MemoryReadAddress slave_readmem[] =
  178. {
  179.     { TOBYTE(0x00000000), TOBYTE(0x000fffff), exterm_slave_videoram_r },
  180.     { TOBYTE(0xc0000000), TOBYTE(0xc00001ff), TMS34010_io_register_r },
  181.     { TOBYTE(0xff800000), TOBYTE(0xffffffff), MRA_BANK4 },
  182.     { -1 }  /* end of table */
  183. };
  184.  
  185. static struct MemoryWriteAddress slave_writemem[] =
  186. {
  187.     { TOBYTE(0x00000000), TOBYTE(0x000fffff), placeholder, &exterm_slave_videoram },
  188. /*{ TOBYTE(0x00000000), TOBYTE(0x000fffff), exterm_slave_videoram_16_w },      OR        */
  189. /*{ TOBYTE(0x00000000), TOBYTE(0x000fffff), exterm_slave_videoram_8_w },       OR        */
  190.     { TOBYTE(0xc0000000), TOBYTE(0xc00001ff), TMS34010_io_register_w },
  191.     { TOBYTE(0xfffffb90), TOBYTE(0xfffffb90), exterm_slave_speedup_w, &exterm_slave_speedup },
  192.     { TOBYTE(0xff800000), TOBYTE(0xffffffff), MWA_BANK4 },
  193.     { -1 }  /* end of table */
  194. };
  195.  
  196.  
  197. static struct MemoryReadAddress sound_dac_readmem[] =
  198. {
  199.     { 0x0007, 0x0007, exterm_sound_dac_speedup_r },
  200.     { 0x0000, 0x07ff, MRA_RAM },
  201.     { 0x4000, 0x4000, soundlatch_r },
  202.     { 0x8000, 0xffff, MRA_ROM },
  203.     { -1 }  /* end of table */
  204. };
  205.  
  206. static struct MemoryWriteAddress sound_dac_writemem[] =
  207. {
  208.     { 0x0000, 0x07ff, MWA_RAM },
  209.     { 0x8000, 0x8000, DAC_0_data_w },
  210.     { 0x8001, 0x8001, DAC_1_data_w },
  211.     { -1 }  /* end of table */
  212. };
  213.  
  214.  
  215. static struct MemoryReadAddress sound_ym2151_readmem[] =
  216. {
  217.     { 0x02b6, 0x02b6, exterm_sound_ym2151_speedup_r },
  218.     { 0x0000, 0x07ff, MRA_RAM },
  219.     { 0x6800, 0x6800, soundlatch_r },
  220.     { 0x7000, 0x7000, gottlieb_cause_dac_nmi_r },
  221.     { 0x8000, 0xffff, MRA_ROM },
  222.     { -1 }  /* end of table */
  223. };
  224.  
  225. static struct MemoryWriteAddress sound_ym2151_writemem[] =
  226. {
  227.     { 0x0000, 0x07ff, MWA_RAM },
  228.     { 0x4000, 0x4000, exterm_ym2151_w },
  229.     { 0x6000, 0x6000, gottlieb_nmi_rate_w },
  230.     { 0xa000, 0xa000, exterm_sound_control_w },
  231.     { -1 }  /* end of table */
  232. };
  233.  
  234.  
  235.  
  236. INPUT_PORTS_START( exterm )
  237.  
  238.     PORT_START      /* IN0 LO */
  239.     PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
  240.     PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START1 )
  241.     PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER1)
  242.     PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER1)
  243.     PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER1)
  244.     PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1)
  245.     PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
  246.     PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
  247.  
  248.     PORT_START      /* IN0 HI */
  249.     PORT_BITX(0x01, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER1, "Aim Left",  KEYCODE_Z, IP_JOY_DEFAULT )
  250.     PORT_BITX(0x02, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER1, "Aim Right", KEYCODE_X, IP_JOY_DEFAULT )
  251.     PORT_BIT( 0xec, IP_ACTIVE_LOW, IPT_UNUSED )
  252.     PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
  253.  
  254.     PORT_START      /* IN1 LO */
  255.     PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN2 )
  256.     PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
  257.     PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER2)
  258.     PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER2)
  259.     PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER2)
  260.     PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2)
  261.     PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
  262.     PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
  263.  
  264.     PORT_START      /* IN1 HI */
  265.     PORT_BITX(0x01, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2, "2 Aim Left",  KEYCODE_H, IP_JOY_DEFAULT )
  266.     PORT_BITX(0x02, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER2, "2 Aim Right", KEYCODE_J, IP_JOY_DEFAULT )
  267.     PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
  268.  
  269.     PORT_START    /* DSW */
  270.     PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) ) /* According to the test screen */
  271.     PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
  272.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  273.     /* Note that the coin settings don't match the setting shown on the test screen,
  274.        but instead what the game appears to used. This is either a bug in the game,
  275.        or I don't know what else. */
  276.     PORT_DIPNAME( 0x06, 0x06, DEF_STR( Coin_A ) )
  277.     PORT_DIPSETTING(    0x06, DEF_STR( 1C_1C ) )
  278.     PORT_DIPSETTING(    0x02, DEF_STR( 1C_2C ) )
  279.     PORT_DIPSETTING(    0x04, DEF_STR( 1C_3C ) )
  280.     PORT_DIPSETTING(    0x00, DEF_STR( 1C_4C ) )
  281.     PORT_DIPNAME( 0x38, 0x38, DEF_STR( Coin_B ) )
  282.     PORT_DIPSETTING(    0x38, DEF_STR( 1C_1C ) )
  283.     PORT_DIPSETTING(    0x18, DEF_STR( 1C_2C ) )
  284.     PORT_DIPSETTING(    0x28, DEF_STR( 1C_3C ) )
  285.     PORT_DIPSETTING(    0x08, DEF_STR( 1C_4C ) )
  286.     PORT_DIPSETTING(    0x30, DEF_STR( 1C_5C ) )
  287.     PORT_DIPSETTING(    0x10, DEF_STR( 1C_6C ) )
  288.     PORT_DIPSETTING(    0x20, DEF_STR( 1C_7C ) )
  289.     PORT_DIPSETTING(    0x00, DEF_STR( 1C_8C ) )
  290.     PORT_DIPNAME( 0x40, 0x40, "Memory Test" )
  291.     PORT_DIPSETTING(    0x40, "Single" )
  292.     PORT_DIPSETTING(    0x00, "Continous" )
  293.     PORT_DIPNAME( 0x80, 0x80, DEF_STR( Free_Play ) )
  294.     PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
  295.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  296. INPUT_PORTS_END
  297.  
  298.  
  299. static struct DACinterface dac_interface =
  300. {
  301.     2,             /* 2 channels on 1 chip */
  302.     { 50, 50 },
  303. };
  304.  
  305. static struct YM2151interface ym2151_interface =
  306. {
  307.     1,            /* 1 chip */
  308.     4000000,    /* 4 MHz */
  309.     { YM3012_VOL(50,MIXER_PAN_LEFT,50,MIXER_PAN_RIGHT) },
  310.     { 0 }
  311. };
  312.  
  313.  
  314. static struct MachineDriver machine_driver_exterm =
  315. {
  316.     /* basic machine hardware */
  317.     {
  318.         {
  319.             CPU_TMS34010,
  320.             40000000/8,    /* 40 Mhz */
  321.             master_readmem,master_writemem,0,0,
  322.             ignore_interrupt,0,  /* Display Interrupts caused internally */
  323.             0,0,&master_config
  324.         },
  325.         {
  326.             CPU_TMS34010,
  327.             40000000/8,    /* 40 Mhz */
  328.             slave_readmem,slave_writemem,0,0,
  329.             ignore_interrupt,0,  /* Display Interrupts caused internally */
  330.             0,0,&slave_config
  331.         },
  332.         {
  333.             CPU_M6502 | CPU_AUDIO_CPU,
  334.             2000000,    /* 2 Mhz */
  335.             sound_dac_readmem,sound_dac_writemem,0,0,
  336.             ignore_interrupt,0    /* IRQ caused when sound command is written */
  337.                                 /* NMIs are triggered by the YM2151 CPU */
  338.         },
  339.         {
  340.             CPU_M6502 | CPU_AUDIO_CPU,
  341.             2000000,    /* 2 Mhz */
  342.             sound_ym2151_readmem,sound_ym2151_writemem,0,0,
  343.             ignore_interrupt,0    /* IRQ caused when sound command is written */
  344.                                 /* NMIs are triggered by a programmable timer */
  345.         }
  346.     },
  347.     60, DEFAULT_60HZ_VBLANK_DURATION,    /* frames per second, vblank duration */
  348.     1,
  349.     0,
  350.  
  351.     /* video hardware, the reason for 263 is that the VCOUNT register is
  352.        supposed to go from 0 to the value in VEND-1, which is 263 */
  353.     256, 263, { 0, 255, 0, 238 },
  354.  
  355.     0,
  356.     4096+32768,0,
  357.     exterm_init_palette,
  358.  
  359.     VIDEO_TYPE_RASTER | VIDEO_MODIFIES_PALETTE,
  360.     0,
  361.     exterm_vh_start,
  362.     exterm_vh_stop,
  363.     exterm_vh_screenrefresh,
  364.  
  365.     /* sound hardware */
  366.     SOUND_SUPPORTS_STEREO,0,0,0,
  367.     {
  368.         {
  369.             SOUND_DAC,
  370.             &dac_interface
  371.         },
  372.         {
  373.             SOUND_YM2151,
  374.             &ym2151_interface
  375.         }
  376.     },
  377.  
  378.     nvram_handler
  379. };
  380.  
  381.  
  382.  
  383. /***************************************************************************
  384.  
  385.   Game driver(s)
  386.  
  387. ***************************************************************************/
  388.  
  389. ROM_START( exterm )
  390.     ROM_REGION( 0x200000, REGION_CPU1 )     /* 2MB for 34010 code */
  391.     ROM_LOAD_ODD(  "v101bg0",  0x000000, 0x10000, 0x8c8e72cf )
  392.     ROM_LOAD_EVEN( "v101bg1",  0x000000, 0x10000, 0xcc2da0d8 )
  393.     ROM_LOAD_ODD(  "v101bg2",  0x020000, 0x10000, 0x2dcb3653 )
  394.     ROM_LOAD_EVEN( "v101bg3",  0x020000, 0x10000, 0x4aedbba0 )
  395.     ROM_LOAD_ODD(  "v101bg4",  0x040000, 0x10000, 0x576922d4 )
  396.     ROM_LOAD_EVEN( "v101bg5",  0x040000, 0x10000, 0xa54a4bc2 )
  397.     ROM_LOAD_ODD(  "v101bg6",  0x060000, 0x10000, 0x7584a676 )
  398.     ROM_LOAD_EVEN( "v101bg7",  0x060000, 0x10000, 0xa4f24ff6 )
  399.     ROM_LOAD_ODD(  "v101bg8",  0x080000, 0x10000, 0xfda165d6 )
  400.     ROM_LOAD_EVEN( "v101bg9",  0x080000, 0x10000, 0xe112a4c4 )
  401.     ROM_LOAD_ODD(  "v101bg10", 0x0a0000, 0x10000, 0xf1a5cf54 )
  402.     ROM_LOAD_EVEN( "v101bg11", 0x0a0000, 0x10000, 0x8677e754 )
  403.     ROM_LOAD_ODD(  "v101fg0",  0x180000, 0x10000, 0x38230d7d )
  404.     ROM_LOAD_EVEN( "v101fg1",  0x180000, 0x10000, 0x22a2bd61 )
  405.     ROM_LOAD_ODD(  "v101fg2",  0x1a0000, 0x10000, 0x9420e718 )
  406.     ROM_LOAD_EVEN( "v101fg3",  0x1a0000, 0x10000, 0x84992aa2 )
  407.     ROM_LOAD_ODD(  "v101fg4",  0x1c0000, 0x10000, 0x38da606b )
  408.     ROM_LOAD_EVEN( "v101fg5",  0x1c0000, 0x10000, 0x842de63a )
  409.     ROM_LOAD_ODD(  "v101p0",   0x1e0000, 0x10000, 0x6c8ee79a )
  410.     ROM_LOAD_EVEN( "v101p1",   0x1e0000, 0x10000, 0x557bfc84 )
  411.  
  412.     ROM_REGION( 0x1000, REGION_CPU2 )     /* Slave CPU memory space. There are no ROMs mapped here */
  413.  
  414.     ROM_REGION( 0x10000, REGION_CPU3 )     /* 64k for DAC code */
  415.     ROM_LOAD( "v101d1", 0x08000, 0x08000, 0x83268b7d )
  416.  
  417.     ROM_REGION( 0x10000, REGION_CPU4 )     /* 64k for YM2151 code */
  418.     ROM_LOAD( "v101y1", 0x08000, 0x08000, 0xcbeaa837 )
  419. ROM_END
  420.  
  421.  
  422. void init_exterm(void)
  423. {
  424.     memcpy (exterm_code_rom,memory_region(REGION_CPU1),code_rom_size);
  425.  
  426.     TMS34010_set_stack_base(0, cpu_bankbase[1], TOBYTE(0x00c00000));
  427.     TMS34010_set_stack_base(1, cpu_bankbase[4], TOBYTE(0xff800000));
  428. }
  429.  
  430.  
  431. GAME( 1989, exterm, 0, exterm, exterm, exterm, ROT0_16BIT, "Gottlieb / Premier Technology", "Exterminator" )
  432.